參數(shù)資料
型號: PCA9674TS,112
廠商: NXP Semiconductors
文件頁數(shù): 7/40頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 20SSOP
標準包裝: 75
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-LSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-SSOP
包裝: 管件
包括: POR
其它名稱: 935283189112
PCA9674TS
PCA9674TS-ND
PCA9674_PCA9674A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 30 May 2013
15 of 40
NXP Semiconductors
PCA9674; PCA9674A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
8.2 Writing to the port (Output mode)
The master (microcontroller) sends the START condition and slave address setting the
last bit of the address byte to logic 0 for the write mode. The PCA9674/74A acknowledges
and the master then sends the data byte for P7 to P0 to the port register. As the clock line
goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by
the PCA9674/74A. If a LOW is written, the strong pull-down turns on and stays on. If a
HIGH is written, the strong pull-up turns on for 12 of the clock cycle, then the line is held
HIGH by the weak current source. The master can then send a STOP or ReSTART
condition or continue sending data. The number of data bytes that can be sent
successively is not limited and the previous data is overwritten every time a data byte has
been sent and acknowledged.
Ensure a logic 1 is written for any port that is being used as an input to ensure the strong
external pull-down is turned off.
Fig 12. Simple quasi-bidirectional I/O
002aah683
VDD
weak 100 A
current source
(inactive when
output LOW)
output HIGH
VSS
output LOW
accelerator
pull-up
P port
P7 - P0
pull-down with
resistor to VSS or
external drive LOW
input LOW
pull-up with
resistor to VDD or
external drive HIGH
input HIGH
Fig 13. Write mode (output)
A5 A4 A3 A2 A1 A0
0
A
SA6
slave address
START condition
R/W
acknowledge
from slave
002aah623
P6
1
P7
data 1
A
acknowledge
from slave
12345678
SCL
9
SDA
A
acknowledge
from slave
write to port
data output from port
tv(Q)
P5
data 2
DATA 2 VALID
P4 P3 P2 P1 P0
P7
P4 P3 P2 P1 P0
P6
P5
0
tv(Q)
DATA 1 VALID
P5 output voltage
Itrt(pu)
IOH
P5 pull-up output current
trst(INT)
INT
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