參數(shù)資料
型號(hào): PCA9672PW,112
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 14/36頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16TSSOP
產(chǎn)品培訓(xùn)模塊: LED Controllers
I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 96
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁(yè)面: 826 (CN2011-ZH PDF)
其它名稱(chēng): 568-4196-5
935282747112
PCA9672PW
PCA9672
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 27 May 2013
21 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Port timing; CL 100 pF (see Figure 13 and Figure 14)
tv(Q)
data output valid time
-
4
-
4
-
4
s
tsu(D)
data input set-up time
0
-
0
-
0
-
s
th(D)
data input hold time
4
-
4
-
4
-
s
Interrupt timing; CL 100 pF (see Figure 13 and Figure 14)
tv(INT)
valid time on pin INT
from port
to INT
-4
-
4
-
4
s
trst(INT)
reset time on pin INT
from SCL
to INT
-4
-
4
-
4
s
Reset timing (see Figure 23)
tw(rst)
reset pulse width
4
-
4
-
4
-
s
trec(rst)
reset recovery time
0
-
0
-
0
-
s
trst
reset time
100
-
100
-
100
-
s
Table 9.
Dynamic characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Fast mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
Rise and fall times refer to VIL and VIH.
Fig 22. I2C-bus timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA
tSU;DAT
tHD;DAT
tf
tBUF
tSU;STA
tLOW
tHIGH
tVD;ACK
tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
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