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參數(shù)資料
型號: PCA9575HF,118
廠商: NXP Semiconductors
文件頁數(shù): 13/38頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24HWQFN
產(chǎn)品培訓模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-HWQFN(4x4)
包裝: 標準包裝
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-4771-6
PCA9575_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 November 2009
20 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
8.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 9).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is dened as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP
condition (P) (see Figure 10).
8.2 System conguration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 11).
Fig 9.
Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 10. Denition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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