參數(shù)資料
型號: PCA9574HR,115
廠商: NXP Semiconductors
文件頁數(shù): 33/33頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16HXQFN
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
標(biāo)準(zhǔn)包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-XFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-UHXQFN
包裝: 標(biāo)準(zhǔn)包裝
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-4936-6
PCA9574
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 April 2012
9 of 33
NXP Semiconductors
PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3
will have no effect on the I/O.
Table 7.
Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
E0.7
R/W
X
not used
6E0.6
R/W
X
5E0.5
R/W
X
4E0.4
R/W
X
3E0.3
R/W
X
2E0.2
R/W
X
1
E0.1
R/W
0*
allows the user to enable/disable pull-up/pull-downs on the
I/O pins
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the I/O
(default value)
1 = enables selection of pull-up/pull-down using
Register 3
0
E0.0
R/W
0*
allows user to enable/disable the bus-hold feature for the I/O
pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
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