參數(shù)資料
型號: PCA9557D,112
廠商: NXP Semiconductors
文件頁數(shù): 4/30頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16SOIC
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 50
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-1060-5
935270674112
PCA9557D
PCA9557
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
12 of 30
NXP Semiconductors
PCA9557
8-bit I2C-bus and SMBus I/O port with reset
Fig 16. Read from register
0
1
A2 A1 A0
0
A
S0
START condition
R/W
acknowledge
from slave
002aad283
A
acknowledge
from slave
SDA
A
P
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
1
A
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
command byte
0
1
A2 A1 A0
0
Remark: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Fig 17. Read input port register
0
1
A2 A1 A0
1
A
S0
START condition
R/W
acknowledge
from slave
002aad284
A
acknowledge
from master
SDA
NA
read from
port
data into
port
P
th(D)
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2
DATA 3
DATA 4
tsu(D)
DATA 1
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