參數(shù)資料
型號(hào): PCA9556
廠商: NXP Semiconductors N.V.
英文描述: Octal SMBus Registered Interface(八位SM總線寄存接口)
中文描述: 八進(jìn)制注冊(cè)的SMBus接口(八位釤總線寄存接口)
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 111K
代理商: PCA9556
Philips Semiconductors
Product specification
PCA9556
Octal SMBus Registered Interface
1998 Dec 18
8
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
DD
Supply voltage
V
I
Input voltage
I
I
DC input current
V
I/O
DC voltage on an I/O as an input other than I/O0
V
I/O0
DC voltage on I/O0 as an input
PARAMETER
CONDITIONS
MIN
–0.5
MAX
+4.6
V
DD
+ 0.5
±
20
V
DD
+ 0.5
4.6
+400
–20
±
20
UNIT
V
V
mA
V
V
μ
A
mA
mA
mA
mA
mW
mW
°
C
°
C
V
SS
– 0.5
V
SS
– 0.5
V
SS
– 0.5
–65
0
I
I/O0
DC input current on I/O0
DC in ut current on I/O0
I
I/O
I
DD
I
SS
P
tot
P
O
T
stg
T
amb
DC output current on an I/O
Supply current
Supply current
Total power dissipation
Power dissipation per output
Storage temperature range
Operating ambient temperature
+150
+70
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.
DC CHARACTERISTICS
V
DD
= 3.0 to 3.6 V; V
SS
= 0 V; T
amb
= 0 to +70
°
C; unless otherwise specified.
SYMBOL
PARAMETER
Supplies
V
DD
Supply voltage
CONDITIONS
MIN
TYP
MAX
UNIT
3.0
3.6
V
I
DD
Supply current
Operating mode; V
DD
= 3.3 V;
no load; V
I
= V
DD
or V
SS
;
f
SCL
= 100 kHz
Standby mode; V
DD
= 3.3 V
no load; V
I
= V
DD
or V
SS
V
= 3.3 V
no load; V
I
= V
DD
or V
SS;
note 1
300
425
μ
A
I
stb
Standby current
25
50
μ
A
V
POR
Power-on reset voltage
1.3
2.4
V
input SCL; input/output SDA
V
IL
LOW level input voltage
V
IH
HIGH level input voltage
I
OL
LOW level output current
I
L
Leakage current
C
I
Input capacitance
I/Os
V
IL
LOW level input voltage
V
IH
HIGH level input voltage
Maximum allowed input current through
protection diode (I/O1 – I/O7)
I
OL
LOW level output current
HIGH level output current except I/O0
I
OH
HIGH level output current on I/O0
HIGH level out ut current on I/O0
–0.5
2.1
3
–1
0.8
V
V
V
DD
+ 0.5
+1
10
V
OL
= 0.4V
V
I
= V
DD
= V
SS
V
I
= V
SS
mA
μ
A
pF
–0.5
2.0
0.8
V
V
V
DD
+ 0.5
I
IHL(max)
V
I
V
DD
or V
I
V
SS
±
400
μ
A
V
OL
= 0.55V; V
DD
= 3.3V
V
OH
= 2.4V; V
DD
= 3.3V
V
DD
= 3.6V; V
OH
= 4.6V
V
DD
= 0V; V
OH
= 3.3V
V
DD
= 3.6V; V
I
= 0 or V
DD
8
4
10
mA
mA
1
1
1
10
10
μ
A
I
L
C
I
C
O
Input leakage current
Input capacitance
Output capacitance
–1
μ
A
pF
pF
Select Inputs A0, A1, A2, and RESET
V
IL
LOW level input voltage
V
IH
HIGH level input voltage
I
LI
Input leakage current
NOTE:
1. The power-on reset circuit resets the SMBus logic with V
DD
<
V
POR
and sets all I/Os to their default values
–0.5
2.0
–1
0.8
V
V
μ
A
V
DD
+ 0.5
1
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