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參數資料
型號: PCA9536D,112
廠商: NXP Semiconductors
文件頁數: 4/22頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 4B 8SOIC
標準包裝: 100
接口: I²C,SM 總線
輸入/輸出數: 4
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
包括: POR
其它名稱: 935277415112
PCA9536D
PCA9536D-ND
PCA9536_5
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
12 of 22
NXP Semiconductors
PCA9536
4-bit I2C-bus and SMBus I/O port
10. Dynamic characteristics
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
Table 10.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
μs
tHD;DAT
data hold time
0
-
0
-
μs
tVD;ACK
data valid acknowledge time
0.3
3.45
0.1
0.9
μs
tVD;DAT
data valid time
300
-
50
-
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
μs
tr
rise time of both SDA and SCL signals
-
1000
20 + 0.1Cb[3]
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 + 0.1Cb[3]
300
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
Port timing
tv(Q)
data output valid time
-
200
-
200
ns
tsu(D)
data input set-up time
100
-
100
-
ns
th(D)
data input hold time
1
-
1
-
μs
Fig 12. Definition of timing
SDA
SCL
002aab271
tf
S
Sr
P
S
tHD;STA
tLOW
tr
tSU;DAT
tf
tHD;DAT
tHIGH tSU;STA
tHD;STA
tSP
tSU;STO
tr
tBUF
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