參數(shù)資料
型號(hào): PCA9516A
廠商: NXP Semiconductors N.V.
英文描述: 5-channel I2C hub
中文描述: 5通道的I2C樞紐
文件頁(yè)數(shù): 6/13頁(yè)
文件大小: 127K
代理商: PCA9516A
Philips Semiconductors
Product data sheet
PCA9516A
5-channel I
2
C hub
2004 Sep 29
6
In order to illustrate what would be seen in a typical application,
refer to Figures 5 and 6. If the bus master in Figure 4 were to write
to the slave through the PCA9516A, we would see the waveform
shown in Figure 5 on Bus 0. This looks like a normal I
2
C
transmission until the falling edge of the 8th clock pulse. At that
point, the master releases the data line (SDA) while the slave pulls it
LOW through the PCA9516A. Because the V
OL
of the PCA9516A is
typically around 0.5 V, a step in the SDA will be seen. After the
master has transmitted the 9th clock pulse, the slave releases the
data line.
On the Bus 1 side of the PCA9516A, the clock and data lines would
have a positive offset from ground equal to the V
OL
of the
PCA9516A. After the 8th clock pulse, the data line will be pulled to
the V
OL
of the slave device that is very close to ground in our
example.
It is important to note that any arbitration or clock stretching events
on Bus 1 require that the V
OL
of the devices on Bus 1 be 70 mV
below the V
OL
of the PCA9516A (see V
OL
– V
ilc
in the DC
Characteristics section) to be recognized by the PCA9516A and
then transmitted to Bus 0.
9th CLOCK PULSE
V
OL
OF MASTER
V
OL
OF PCA9516A
2 V/DIV
SW02250
Figure 5. Bus 0 waveform
9th CLOCK PULSE
V
OL
OF SLAVE
V
OL
OF PCA9516A
2 V/DIV
SW02251
Figure 6. Bus 1 waveform
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