參數(shù)資料
型號(hào): PCA9506DGG,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 15/34頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 35
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁(yè)面: 824 (CN2011-ZH PDF)
其它名稱: 568-3354-5
935280798512
PCA9506DGG
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
22 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
[1]
VDD must be lowered to 0.2 V in order to reset part.
12. Dynamic characteristics
Inputs A0, A1, A2
VIL
LOW-level input voltage
0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD
-5.5
V
ILI
input leakage current
1-
+1
μA
Ci
input capacitance
-
3.5
5
pF
Table 10.
Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 11.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
μs
tHD;DAT
data hold time
0
-
0
-
ns
tVD;ACK
data valid acknowledge time[2]
0.1
3.45
0.1
0.9
μs
tVD;DAT
data valid time[3]
0.1
3.45
0.1
0.9
μs
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
μs
tf
fall time of both SDA and SCL
signals
-
300
20 + 0.1Cb[6]
300
ns
tr
rise time of both SDA and SCL
signals
-
1000
20 + 0.1Cb[6]
300
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
Port timing
ten
enable time
output
-
80
-
80
ns
tdis
disable time
output
-
40
-
40
ns
tv(Q)
data output valid time
-
250
-
250
ns
tsu(D)
data input set-up time
100
-
100
-
ns
th(D)
data input hold time
0.5
-
0.5
-
μs
Interrupt timing
tv(INT_N)
valid time on pin INT_N
-
4
-
4
μs
trst(INT_N)
reset time on pin INT_N
-
4
-
4
μs
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