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參數(shù)資料
型號(hào): PCA9500BS,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 22/26頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16HVQFN
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出: 無(wú)
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.5 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 16-HVQFN
包裝: 標(biāo)準(zhǔn)包裝
包括: EEPROM,POR
產(chǎn)品目錄頁(yè)面: 824 (CN2011-ZH PDF)
其它名稱: 568-3351-6
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
5 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7.
Functional description
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9500 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware selectable address pins.
The last bit of the address byte denes the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.2 Control register
The PCA9500 contains a single 8-bit register called the Control register, which can be
written and read via the I2C-bus. This register is sent after a successful acknowledgment
of the slave address. It contains the I/O operation information.
Fig 5.
Simplied schematic diagram of each I/O
002aae588
write pulse
read pulse
D
CI
S
FF
Q
power-on reset
data from shift register
100
A
VDD
IO0 to IO7
VSS
D
CI
S
FF
Q
data to shift register
to interrupt logic
a. I/O expander
b. Memory
Fig 6.
PCA9500 slave addresses
002aae589
0
1
0
A2
A1
A0 R/W
fixed
slave address
hardware
programmable
002aae590
1
0
1
0
A2
A1
A0 R/W
fixed
slave address
hardware
programmable
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PCA9500D,118-CUT TAPE 制造商:NXP 功能描述:PCA9500 Series 8-Bit I2C and SMBus I/O Port w/ 2-kbit EEPROM - SOIC - 16