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參數(shù)資料
| 型號(hào)： | PCA8550 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM |
| 中文描述： | 4位multiplexed/1-bit鎖存5位的I2C EEPROM的 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | PCA8550 |
Philips Semiconductors
Product specification
PCA8550
4-bit multiplexed/1-bit latched 5-bit I
2
C EEPROM
1998 Sep 29
3
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
I
2
C SCL
I
2
C bus clock
2
I
2
C SDA
Bi-directional I
2
C bus data
3
OVERRIDE#
Forces all outputs to logic 0
4
MUX_IN A
5
MUX_IN B
External inputs to multiplexer
External in uts to multi lexer
6
MUX_IN C
7
MUX_IN D
8
GND
Common ground voltage rail
9
MUX_OUT D
10
MUX_OUT C
2 5V multiplexed output
2.5V multi lexed out ut
11
MUX_OUT B
12
MUX_OUT A
13
MUX_SELECT
Selects MUX_IN inputs or
register contents for
MUX_OUT outputs
14
NON_MUXED_OUT
TTL-level output from
non-volatile memory
15
WP
Non-volatile register
write-protect
16
V
CC
Positive voltage rail
FUNCTION TABLE
Table 1. Function table
OVERRIDE
#
MUX_SELECT
MUX_OUT
OUTPUTS
NON_MUXED_OUT
OUTPUT
0
0
All 0’s
All 0’s
0
1
MUX_IN
inputs
Latched
NON_MUXED_OUT
1
1
0
From non-
volatile
register
From non-volatile
register
1
1
MUX_IN
inputs
From non-volatile
register
NOTE
1. Latched NON_MIXED_OUT state will be the value present on
the NON_MUXED_OUT output at the time of the MUX_SELECT
input transitioned from a logic 0 to a logic 1 state.
I
2
C Interface
Communicating with this device is initiated by sending a valid address on the I
2
C bus. The address format (see FIgure 1) is a fixed unique 7-bit
value followed by a 1-bit read/write value which determines the direction of the data transfer.
SW00218
MSB
LSB
1
1
1
0
R/W#
1
0
0
Figure 1. I
2
C Address Byte
Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write
data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read
from the register if the bit is logic 1. The three high-order bits (see FIgure 2) are logic 0. The next bit is data which is non-multiplexed. The low
four bits are the data which will be multiplexed. A write with any of the first three bits non-zero will be aborted.
NOTE:
1. To ensure data integrity, the non-volatile register must be internally write protected when V
CC
to the I
2
C bus is powered down or V
CC
to the
component is dropped below normal operating levels.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCA8550 | NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE |
| PCA8550D | NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE |
| PCA8550DB | NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE |
| PCA8550PW | NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE |
| PCA8575 | Remote 16-bit I/O expander for I2C-bus with interrupt |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA8550_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE |
| PCA8550D | 功能描述:寄存器 4-BIT 1-OF-2 I2C MULTIPLEXER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PCA8550D,112 | 功能描述:寄存器 4-BIT 1-OF-2 I2C RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PCA8550D,118 | 功能描述:寄存器 4-BIT 1-OF-2 I2C RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PCA8550DB | 功能描述:寄存器 4-BIT 1-OF-2 I2C MULTIPLEXER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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