參數(shù)資料
型號: PCA84C840
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with OSD and VST(帶OSD 和 VST的8位微控制器)
中文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42
文件頁數(shù): 24/40頁
文件大小: 233K
代理商: PCA84C840
1996 Nov 29
24
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
12.6.2
D
ERIVATIVE REGISTERS
LINE 0A
AND
LINE 0B
Table 13
Derivative register LINE 0A (address 41H)
Table 14
Description of LINE 0A bits
Table 15
Derivative register LINE 0B (address 42H)
Table 16
Description of LINE 0B bits
REGISTER
FUNCTION
LINE 0A
LINE 0B
Determine the character size and vertical position of Row 0 (the first display row).
Determine the horizontal position of Row 0 and the selection of background and blanking functions.
7
6
5
4
3
2
1
0
SZ01
SZ00
VP05
VP04
VP03
VP02
VP01
VP00
BIT SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
SZ01
SZ00
VP05
VP04
VP03
VP02
VP01
VP00
Character size.
The state of these two bits enable one of four possible character sizes to be
selected for Row 0. Character sizes include background. See Table 23.
Vertical position control.
The vertical position of Row 0 is selected by the state of the 6 bits, VP00 to VP05.
For details see Section 12.7.1 “Vertical position”.
7
6
5
4
3
2
1
0
BLK0
VB0
HP05
HP04
HP03
HP02
HP01
HP00
BIT SYMBOL
DESCRIPTION
7
BLK0
Blanking
. This bit enables or disables the character display. When BLK0 is set to:
Logic 1, the outputs VOW1, VOW2, VOW3 and VOB are enabled; characters are displayed.
Logic 0, the outputs VOW1, VOW2, VOW3 and VOB are disabled; no characters are displayed.
Background.
This bit determines whether the background display is selected or not.
The visual effect of background versus no background is shown in Fig.26. When VB0 is set to:
Logic 1, the characters in this row are displayed with background.
Logic 0, the background is disabled and only the characters are displayed.
Horizontal position control
.
These 6 bits determine the start position of Row 0.
The horizontal position control is only active during OSDC clock cycles.
For details Section 12.7.2 “Horizontal position” and Fig.25.
6
VB0
5
4
3
2
1
0
HP05
HP04
HP03
HP02
HP01
HP00
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