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參數(shù)資料
| 型號(hào)： | PCA84C641 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with OSD and VST(帶OSD 和 VST的8位微控制器) |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42 |
| 文件頁(yè)數(shù)： | 12/40頁(yè) |
| 文件大?。?/td> | 233K |
| 代理商： | PCA84C641 |
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1996 Nov 29
12
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
9
VST CONTROL
9.1
14-bit PWM DAC
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
14-bit counter
Two 7-bit DAC interface data latches (VSTH and VSTL)
One 14-bit DAC data latch (VSTREG)
Pulse control.
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
Logic 1, sets the TDAC output to the default polarity
Logic 0, inverts the TDAC output.
9.1.1
14-
BIT COUNTER
The counter is continuously running and is clocked by f
0
.
The period of the clock,
The repetition time for one complete cycle of the counter:
The repetition time for one cycle of the lower 7-bits of the
counter is:
Therefore, the number of t
sub
periods in a complete
cycle t
r
is:
9.1.2
D
ATA AND INTERFACE LATCHES
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
VSTH are used for coarse adjustment
VSTL are used for fine adjustment.
At the beginning of the first t
sub
period following the loading
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one t
sub
period is needed to
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) t
sub
periods
should be allowed before beginning the next sequence.
t
0
f
XTAL
----3
=
t
r
t
0
16384
×
=
t
sub
t
0
128
×
=
N
t
---------------------------
16384
128
×
t
0
128
=
=
9.2
Coarse adjustment
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each t
sub
period.
It will remain LOW until the time
elapsed and then will go HIGH and remain so until the next
t
sub
period starts.
has
9.3
Fine adjustment
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (t
subn
).
These additional pulses have a width of t
0
.
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the t
subn
, at the start of which
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination
of
VSTL = 1111110: sub-period 64, and
VSTL = 1111011: sub-periods 16, 48, 80 and 112,
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output is as shown in Fig.13.
Table 3
Additional pulse distribution
LOWER
7 BITS
(VSTL)
ADDITIONAL PULSE IN
SUB-PERIODS t
subn
111111
0
11111
0
1
1111
0
11
111
0
111
11
0
1111
1
0
11111
0
111111
64
32, 96
16, 48, 80, 112
8, 24, 40, 56, 72, 88, 104, 120
4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124
2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126
1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127
t
0
VSTH
1
+
(
)
×
[
]
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