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參數(shù)資料
| 型號： | PC9RS08LE4CWL |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 0K |
| 描述： | MCU 8BIT 4K FLASH W/ LCD 28-SOIC |
| 標準包裝： | 26 |
| 系列： | RS08 |
| 核心處理器： | RS08 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | SCI |
| 外圍設(shè)備： | LCD，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 托盤 |
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Internal Clock Source (ICS) Characteristics
MC9RS08LE4 MCU Data Sheet, Rev. 3
Freescale Semiconductor
17
3.9
Internal Clock Source (ICS) Characteristics
3.10
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85
°C Ambient)
Num
C
Characteristic
Symbol
Min
Typical1
1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
Max
Unit
1C
Square wave input clock frequency (EREFS = 0)
FLL bypass external (CLKS = 10)
FLL engaged external (CLKS = 00)
fextal
0
0.03125
—
20
5
MHz
2
C Average internal reference frequency - untrimmed
fint_ut
25
31.25
41.66
kHz
3
C Average internal reference frequency - trimmed
fint_t
31.25
39.0625
kHz
4
C DCO output frequency range — untrimmed
fdco_ut
12.8
16
21.33
MHz
5
C DCO output frequency range — trimmed
fdco_t
16
20
MHz
6C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature
Δfdco_res_t
——
±0.2
%fdco
7C
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
——
±2%fdco
8
C FLL acquisition time 3,2
2 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
tacquire
——
1
ms
9C
Long term Jitter 3 of DCO output clock (averaged
over 2 ms interval)
3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
CJitter
——
0.6
%fdco
Table 11. Control Timing
Num
C
Parameter
Symbol
Min
Typical
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
0—
10
MHz
2
D
Real time interrupt internal oscillator period
tRTI
700
1000
1300
μs
3
D
External RESET pulse width1
1 This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be
recognized.
textrst
150
—
ns
4
D
KBI pulse width2
tKBIPW
1.5 tcyc
——
ns
5
D
KBI pulse width in stop1
tKBIPWS
100
—
ns
6
C
Port rise and fall time (load = 50 pF)3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
11
35
—
ns
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