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參數(shù)資料
| 型號： | PC755BMZFU400LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BMZFU400LD |
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18/48
PC755B/745B
3.3. Recommendated operating conditions
Table 5. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit
Core supply voltage
Vdd
2.0v
100mV
V
PLL supply voltage
AVdd
2.0v
100mV
V
L2 DLL supply voltage
L2AVdd
2.0v
100mV
V
Processor bus supply
voltage
BVSEL = 0
OVdd
1.8v
2.0
100mV or
100mV
V
BVSEL = 1
OVdd
3.3v
165mV
V
L2 bus supply voltage
L2VSEL = 0
L2OVdd
1.8v
2.0
100mV or
100mV
V
L2VSEL = 1
L2OVdd
3.3v
165mV
V
Input voltage
Processor bus
V
in
GND to OVdd
V
L2 Bus
V
in
GND to L2OVdd
V
JTAG Signals
V
in
GND to OVdd
V
Die-junction temperature
T
j
-55 to 125
o
C
Note :
These are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
3.4. Thermal characteristics
3.4.1. Package characteristics
Table 6 provides the package thermal characteristics for the PC755B.
Table 6. Package Thermal Characteristics
Characteristic
Symbol
Value
Rating
PBGA package thermal resistance, junction-to-case thermal resistance (typical)
θ
JC
0.03
C/W
PBGA package thermal resistance, die junction-to-lead thermal resistance (typical)
θ
JB
θ
JA
12
C/W
PBGA package typical thermal resistance, die junction-to-ambient resistance
(convection only on 2S2P board)
33
C/W
PBGA package thermal resistance, die junction-to-ambient resistance (100 ft/min
airflow on 2S2P board)
θ
JA
30
C/W
Note:
Refer to Section 3.4.3. , “Thermal Management Information,” for more details about thermal management.
The board designer can choose between several types of heat sinks to place on the PC755B. There are several commercially-avail-
able heat sinks for the PC755B provided by the following vendors:
For the exposed-die packaging technology, shown in Table 5, the intrinsic conduction thermal resistance paths are as follows :
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
The die junction-to-ball thermal resistance
Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal
interface material), and finally to the heat sink where it is removed by forced-air convection.
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