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| 型號： | PC7457VGU1200N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7457VGU1200N |
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35
PC7457/47 [Preliminary]
5345B–HIREL–02/04
IEEE 1149.1 AC Timing
Specifications
Table 15
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure
19 through Figure 22 on page 37.
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-
tion. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (see Figure 18).
Time-of-flight delays must be added for trace lengths, vias and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC7457.
Figure 18.
Alternate AC Test Load for the JTAG Interface
Table 15.
JTAG AC Timing Specifications (Independent of SYSCLK)
(1)
at Recommended Operating Conditions
(see Table 3 on page 12)
Symbol
Parameter
Min
Max
Unit
f
TCLK
TCK frequency of operation
0
33.3
MHz
t
TCLK
TCK cycle time
30
–
ns
t
JHJL
TCK clock pulse width measured at 1.4V
15
–
ns
t
JR
and t
JF
TCK rise and fall times
0
2
ns
t
TRST
(2)
TRST assert time
25
–
ns
t
DVJH
t
IVJH
(3)
Input Setup Times:
Boundary-scan data
TMS, TDI
4
0
–
–
ns
t
DXJH
t
IXJH
(3)
Input Hold Times:
Boundary-scan data
TMS, TDI
20
25
–
–
ns
t
JLDV
t
JLOV
(4)
Valid Times:
Boundary-scan data
TDO
4
4
20
25
ns
t
JLDX
t
JLOX
(4)
Output hold times:
Boundary-scan data
TDO
TBD
TBD
TBD
TBD
t
JLDZ
t
JLOZ
(4)(5)
TCK to output high impedance:
Boundary-scan data
TDO
3
3
19
9
ns
Output
Z0 = 50
RL = 50
OVDD/2
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