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參數(shù)資料
| 型號： | PC33991DHR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, PDSO24 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 660K |
| 代理商： | PC33991DHR2 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33991
3
Pin Functions
Pin
Number
Pin Name
Description
1
COS0+
H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins
linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant operation.
2
COS0-
H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins linearly
drive the sine and cosine coils of two separate stepper motors to provide four-quadrant operation.
3
SIN0+
H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins linearly
drive the sine and cosine coils of two separate stepper motors to provide four-quadrant operation.
4
SIN0-
H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins linearly
drive the sine and cosine coils of two separate stepper motors to provide four-quadrant operation.
5-8
GND
Ground. These pins serve as the ground for the source of the low-side output transistors as well as the logic portion
of the device. They also help dissipate heat from the device.
9
CS
Chip Select. This pin is connected to a chip select output of a LSI IC. This IC controls which device is addressed by
pulling the CS pin of the desired device low, enabling the SPI communication with the device, while other devices on
the serial link keep their serial outputs tri-stated. This input has an internal active pull-up and requires CMOS logic
levels. This pin is also used to calibrate the internal clock.
10
SCLK
Serial Clock. This pin is connected to the SCLK pin of the master device and acts as a bit clock for the SPI port. It
transitions one time per bit transferred at an operating frequency, fSPI, defined in the Coil Output Timing Table. It is
idle between command transfers. The pin is 50 percent duty cycle, with CMOS logic levels. This signal is used to
shift data to and from the device.
11
SO
Serial Output. This pin is connected to the SPI Serial Data Input pin of the master device, or to the SI pin of the next
device in a daisy chain. This output will remain tri-stated unless the device is selected by a low CS signal. The output
signal generated will have CMOS logic levels and the output data will transition on the rising edges of SCLK. The
serial output data provides status feedback and fault information for each output and is returned MSB first when the
device is addressed.
12
SI
Serial Input. This pin is connected to the SPI Serial Data Output pin of the master device from which it receives
output command data. This input has an internal active pull-down requiring CMOS logic levels. The serial data
transmitted on this line is a 16-bit control command sent MSB first, controling the gauge functions. The master
ensures data is available on the falling edge of SCLK.
13
RTZ
Multiplexed Output. This multiplexed output pin of the non-driven coil during an RTZ event.
14
VDD
Voltage. This SPI and logic power supply input will work with 5.0 V supplies.
COS1+
GND
VPWR
RST
VDD
RTZ
COS1-
SIN1+
SIN1-
COS0+
GND
CS
SCLK
SI
COS0-
SIN0+
SIN0-
SO
5
6
7
8
9
10
11
12
2
3
4
24
20
19
18
17
16
15
13
23
22
21
14
1
24 Wide Body SOIC
Thermally Enhanced Lead Frame
RJ-LEAD =15 C/W
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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