參數(shù)資料
型號(hào)： PC33926PNB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： BRUSHLESS DC MOTOR CONTROLLER, 5 A, PQCC32
封裝： 8 X 8 MM, 2.10 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-251AADDB-1, QFN-32
文件頁(yè)數(shù)： 25/25頁(yè)
文件大?。?/td> 778K
代理商： PC33926PNB
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
33926
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V
≤ VPWR ≤ 28 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (21)
fPWM
–
20
kHz
Maximum Switching Frequency During Current Limit Regulation (22)
fMAX
–
20
kHz
Output ON Delay (23)
VPWR = 14 V
tDON
–
18
s
Output OFF Delay (23)
VPWR = 14 V
tDOFF
–
12
s
ILIM Output Constant-OFF Time (24)
tA
15
20.5
32
s
ILIM Blanking Time (25)
tB
12
16.5
27
s
Disable Delay Time (26)
tDDISABLE
–
8.0
s
Output Rise and Fall Time (27)
SLEW = SLOW
SLEW = FAST
tF, tR
1.5
0.2
3.0
–
6.0
1.45
s
Short Circuit/Overtemperature Turn-OFF (Latch-OFF) Time (28) (29)
tFAULT
–
8.0
s
Power-ON Delay Time (29)
tPOD
–
1.0
5.0
ms
Output MOSFET Body Diode Reverse Recovery Time (29)
tRR
75
100
150
ns
Charge Pump Operating Frequency (29)
fCP
–
7.0
–
MHz
Notes
21.
The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to
SLOW should be limited to frequencies < 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side
MOSFETs.
22.
The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
23.
Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5V on the input signal to the 80% point of the
output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5V on the input signal to the 20% point of the output
response signal. See Figure 4, page 10.
24.
The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
25.
The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
26.
Disable Delay Time measurement is defined in Figure 5, page 10.
27.
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 14 V,
RLOAD = 3.0 ohm. See Figure 6, page 10.
28.
Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short circuit currents
possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160
°C will cause the output current limit threshold to “fold back”,
or decrease, until ~175
°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
29.
Parameter is Guaranteed By Design.
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