參數(shù)資料
型號： PC33702DWB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 穩(wěn)壓器
英文描述： 6 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO32
封裝： PLASTIC, SOIC-32
文件頁數(shù)： 15/24頁
文件大?。?/td> 841K
代理商： PC33702DWB
33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
22
APPLICATION INFORMATION
Figure 20. Simplified Block Diagram and Typical Application
50 uF
Buck
Control
Logic
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
INV
EN2
GND
0.8V
R
b
(2)
EN1
SoftSt
CLKSYN
Supply
Voltage
VOUT = 1.8V
VIN2
Buck
HS
&
LS
Driver
VBST
+
-
Vref
Power
Enable
8.0V
VBST
Boost
Control
VBD
10uF
VDDI
LDRV
Vref
LFB
CS
LDO
VLDO = 2.5V
@ 1.0A
+3.3V
RT
RESET
Reset
to MCU
VLDO
Supply
Voltage
+3.3V
VDDI
R
S
SDA
SCL
Ct
PGND
Reset
R
F
4.7 uH
10uH
VIN1
VIN
BOOT
VOUT
VLDO
C
B
LCMP
VBST
L1
C
O
C
IN
Vref
VDDI
Q2
Q1
(2)
(4)
ADDR
I2C
Interface
Rt
I2C
Control
I2C
Control
C
LDO
5 x 2.2 uF
C
BST
D
B
Q
LDO
L
BST
0.1uF
VDDI
R
pd
10k
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
C
IN
VBST
Linear
Regulator
Control
I-lim
+3.3V
or
VOUT
100pF
1.5k
2 x 10 uF
10uF
6.8nF
?pF
?k
?
(Optional)
5.1k
100k
100nF
1.0 uF
0.068 R
@
Pow. Seq.
?k
Q3
Q4
INV
LFB
50 uF
Buck
Control
Logic
Buck
Control
Logic
+
-
+
-
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
INV
EN2
GND
0.8V
R
b
(2)
EN1
SoftSt
CLKSYN
Supply
Voltage
VOUT = 1.8V
VIN2
Buck
HS
&
LS
Driver
Buck
HS
&
LS
Driver
VBST
+
-
+
-
Vref
Power
Enable
8.0V
VBST
Boost
Control
Boost
Control
VBD
10uF
VDDI
LDRV
Vref
LFB
CS
LDO
VLDO = 2.5V
@ 1.0A
+3.3V
RT
RESET
Reset
to MCU
VLDO
Supply
Voltage
+3.3V
VDDI
R
S
SDA
SCL
Ct
PGND
Reset
R
F
4.7 uH
10uH
VIN1
VIN
BOOT
CLKSEL
VOUT
VLDO
C
B
LCMP
VBST
L1
C
O
C
IN
Vref
VDDI
Q2
Q1
(2)
(4)
ADDR
I2C
Interface
Rt
I2C
Control
I2C
Control
C
LDO
5 x 2.2 uF
C
BST
D
B
Q
LDO
L
BST
0.1uF
VDDI
R
pd
10k
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
C
IN
VBST
Linear
Regulator
Control
I-lim
Linear
Regulator
Control
I-lim
+3.3V
or
VOUT
100pF
1.5k
2 x 10 uF
10uF
6.8nF
?pF
?k
?
(Optional)
5.1k
100k
100nF
1.0 uF
0.068 R
@
Pow. Seq.
?k
Q3
Q4
INV
LFB
3.0 A
VIN1
VIN
VBST
VDDI
VBST
VDDI
VBST
VIN2
VOUT
PWR Seq.
VBST
VDDI
VBST
VLDO
VOUT
VDDI
VBD
VBST
PWR Seq.
4.7
H
0.1
F
5 x 2.2
F
10
H
10
F
10
F
VLDO
50
F
+3.3 V
Supply
Voltage
+3.3 V
Supply
Voltage
VOUT = 1.8 V
@ 3.0 A
VLDO = 2.5 V
@ 1.0 A
VLDO
+3.3 V or
RESET
to MCU
2 x 10
F
ILIM
Rt
Ct
I2C
I2C
Watchdog Timer
I2C
F
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sc
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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