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參數(shù)資料
| 型號： | PC33394DWB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.2 A SWITCHING CONTROLLER, 220 kHz SWITCHING FREQ-MAX, PDSO54 |
| 封裝： | PLASTIC, SOIC-54 |
| 文件頁數(shù)： | 13/51頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PC33394DWB |
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33394
20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 5. 33394 Timing Diagram
VDDH = 5.0V
VDD3_3 = 3.3V*
VDDL = 2.6V
VKAM = 2.6V
2.6V
0.7
ms
0.7
ms
0.7
ms
HRT DELAY
VDDH, VDDA,
VFLASH5
KAPWR,
VDDSRAM1,2,3
VDDRTC
PORESET
IRQ0
HRESET
MPC56X
VDDH
VDD3_3
VDDL
VIGN
VKAM
/PORESET
/PRERESET
/HRESET
10ms
3
2
1
4
5
6
8
10
11
9
7
33394
Output
Supply Input
NVDDL, QVDDL,
VDD, VDDSYN,
VDDF
5.0V
2.6V
* VDD3_3 = 3.3V (not used by MPC56x)
1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms.
2 VIGN is applied, 33394 starts power up sequence.
3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay
programmable by an external capacitor and resistor, HRT pin).
4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated.
5 /HRESET is asserted 0.7
ms after /PRERESET
6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released
(with an HRT delay).
7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET
with 0.7
ms delay) are asserted – see Note 1.
8 33394 initiates power down sequence.
9 Fault on VKAM removed, the 33394 initiates the start up sequence.
10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT
delay).
11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed.
Figure 6. 33394 Power Up/Down Sequence
VDDH = 5.0 V
VDD3_3 = 3.3 V
VDDL = 2.6 V*
POWER UP SEQUENCE
POWER DOWN SEQUENCE
0 V
*NOTE: VDDL = 2.6 V for MPC565
LESS THAN 3.1 V
* VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.
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