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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3)
MC9S12XDP512 Data Sheet, Rev. 2.17
166
Freescale Semiconductor
5.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
ATDD47H
10-BIT
8-BIT
0
0
0
0
0
0
0
0
0
0
0
0
BIT 9 MSB
0
BIT 8
0
W
ATDD47L
10-BIT
BIT 7
BIT 7 MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
BIT 0
BIT 0
8-BIT
7
0
6
0
5
0
4
0
3
0
2
1
0
R
W
WRAP2
WRAP1
WRAP0
Reset
0
0
0
0
0
1
1
1
= Unimplemented or Reserved
Figure 5-3. ATD Control Register 0 (ATDCTL0)
Table 5-1. ATDCTL0 Field Descriptions
Field
Description
2–0
WRAP[2:0]
Wrap Around Channel Select Bits
— These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
Table 5-2
.
Table 5-2. Multi-Channel Wrap Around Coding
WRAP2
WRAP1
WRAP0
Multiple Channel Conversions (MULT = 1)
Wrap Around to AN0 after Converting
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 5 of 5)