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Chapter 16 Interrupt (S12XINTV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
600
Freescale Semiconductor
16.3.1
Register Descriptions
This section describes in address order all the XINT registers and their individual bits.
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0121
IVBR
R
W
IVB_ADDR[7:0]
0x0126
INT_XGPRIO
R
W
0
0
0
0
0
XILVL[2:0]
0x0127
INT_CFADDR
R
W
INT_CFADDR[7:4]
0
0
0
0
0x0128
INT_CFDATA0
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x0129
INT_CFDATA1
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x012A
INT_CFDATA2
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x012B
INT_CFDATA3
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x012C INT_CFDATA4
R
W
0
0
0
0
PRIOLVL[2:0]
0x012D INT_CFDATA5
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x012E
INT_CFDATA6
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
0x012F
INT_CFDATA7
R
W
RQST
0
0
0
0
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 16-2. XINT Register Summary