參數(shù)資料
型號(hào): PC28F256J3C-115
廠商: Intel Corp.
英文描述: Intel StrataFlash Memory (J3)
中文描述: 英特爾StrataFlash存儲(chǔ)器(J3)
文件頁(yè)數(shù): 63/72頁(yè)
文件大小: 905K
代理商: PC28F256J3C-115
256-Mbit J3 (x8/x16)
Datasheet
63
0606_09
Figure 22. Block Erase Flowchart
Start
Read
Status Register
SR.7 =
Erase Flash
Block(s) Complete
0
1
Full Status
Check if Desired
Suspend Erase
Issue Single Block Erase
Command 20H, Block
Address
Suspend
Erase Loop
Write Confirm D0H
Block Address
Yes
No
Bus
Operation
Command
Comments
Write
Erase Block
Data = 20H
Addr = Block Address
Data = D0H
Addr = X
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write (Note 1)
Erase
Confirm
Read
Standby
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
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