參數(shù)資料
型號: PC100-222-620
廠商: SIEMENS AG
英文描述: KPT 3C 3#20 SKT PLUG
中文描述: 3.3 2米x 64/72-Bit一銀行內(nèi)存模塊3.3 4米× 64/72-Bit 2銀行內(nèi)存模塊
文件頁數(shù): 1/17頁
文件大?。?/td> 104K
代理商: PC100-222-620
Semiconductor Group
1
3.3V 2M x 64/72-Bit 1 BANK SDRAM Module
3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
168 pin unbuffered DIMM Modules
HYS64/72V2200GU-8/-10
HYS64/72V4220GU-8/-10
168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation
Optimized for byte-write non-parity or ECC applications
JEDEC standard Synchronous DRAMs (SDRAM)
Fully PC board layout compatible to INTEL’ Rev. 1.0 module specification
SDRAM Performance:
Programmed Latencies :
Single +3.3V(
±
0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E
2
PROM
Utilizes 2M x 8 SDRAMs in TSOPII-44 packages
4096 refresh cycles every 64 ms
133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads
-8
-8-3
-10
Units
f
CK
Clock frequency (max.)
100
100
66
MHz
t
AC
Clock access time
6
6
8
ns
Product Speed
CL
tRCD
tRP
-8
PC100
2
2
2
-8-3
PC100
3
2
3
-10
PC66
2
2
2
6.98
相關(guān)PDF資料
PDF描述
PC100-323-620 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
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