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參數(shù)資料
| 型號： | PBA31301/2S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA34 |
| 封裝： | SOBGA-34 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 812K |
| 代理商： | PBA31301/2S |
9
PBA 313 01
EN/LZT 146 65 R3B Ericsson Microelectronics AB, October 2001
Register name
# bits
R or W
Address
Value at reset
Recommended value
VCO/DAFC/Delay
8
W
0100012 = 1710
0 0 0 0 0X0 0
1111 10112 = 25110
Channel
8
W
0100102 = 1810
0 0 0 0 0 0 1 0
RSSI
5
R
XXXUUUUU
XO-trim
6
W
0100112 = 1910
XX0 0 0 0 0 0
ID
8
R
0 0 0 1VVVV
LPO-hi
1
W
0101012 = 2010
XXXXXXX0
LPO-lo
8
W
0101002 = 2110
0 0 0 0 0 0 0 0
Control
7
W
0101102 = 2210
X1 0 0 0 0XX
Bit two set to 1 to enable SYS_CLK_REQ
Modulation
8
W
0101112 = 2310
0 0 0 0 0 0 0 0
0100 00002 = 6410
Current
3
W
0110002 = 2410
0 0 0XXXXX
0000 00002 = 010
Enable
8
W
0110012 = 2510
UUUUUUUU
1011 11112 = 19110
W = Writable, R = Readable, X = Not applicable, U = Undefined, V = Version number
Serial interface example
Writing the value 77 to the Channel register selects Bluetooth
channel 75 (i.e. 2477 MHz) for transmission. This will simulta-
neously read the RSSI measurement for the latest received
packet header. The normal operation sequence is:
Point out the Channel register, this is done by performing
an IR-scan. The SI_CMS signal should be controlled as
shown in figure 10. When in the Shift-IR state the value
010010 should be shifted in on the SI_CDI input (LSB first).
When in the Run Control/Idle state the Instruction Register
is updated.
Write the new channel value, this is done by performing
a DR-scan. The SI_CMS signal should be controlled as
shown in figure 10. When in the Shift-DR state, SI_CDI=
01001101 should be shifted in (LSB first). When in the Run
Control/Idle state the Channel register is updated.
If no other register has been addressed then the Channel
register contents are still in the IR, therefore only a new
DR-scan needs to be done to change to another frequency
channel.
Design Considerations
Power-up sequence
The start-up sequence is as follows, see figure 11 for typical
timing:
1. The start-up sequence starts with a Power-On-Reset
(POR_EXT) or by applying power to VCC. This resets all the
registers in the radio controller.
2. The LPO_CLK starts to oscillate.
Figure 10. Reading and updating a data register. A data register is selected by entering the Shift IR state using SI_CMS, and
transferring the appropriate bit code to the instruction register using SI_CDI (I[5:0]=01YYYY, where YYYY is the address of the
register). Moving to the Shift-DR state, eight bits of register data can then be transferred on SI_CDI and SI_CDO. The data register
selected by the instruction register is updated when the SI controller enters the Update-DR state. At the end of the data register
access, the SI controller is once again held in the Run Control/Idle state.
1
5
10
15
20
5
SI_CLK
SI_CMS
I0
I1
I2
I3
I4
I5
D0 D1 D2 D3 D4 D5 D6 D7
SI_CDI
i0
i1
i2
i3
i4
i5
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SI_CDO
Se
le
ct
D
R
-S
ca
n
R
un
C
on
tr
ol
/Id
le
C
ap
tu
re
IR
Se
le
ct
IR
-S
ca
n
Sh
ift
IR
U
pd
at
e
IR
Ex
it
IR
C
ap
tu
re
D
R
Se
le
ct
D
R
-S
ca
n
Sh
ift
D
R
U
pd
at
e
D
R
Ex
it
D
R
un
C
on
tr
ol
/Id
le
JTAG
controller
state
Table 5. Data registers in the radio controller.
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