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參數(shù)資料
| 型號： | PALLV22V10Z-25PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:18; No. Strands x Strand Size:19 x 30; Jacket Color:Orange; Approval Bodies:UL; Approval Categories:UL AWM Style 1180; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/5 Type EE RoHS Compliant: Yes |
| 中文描述： | EE PLD, 25 ns, PDIP24 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 380K |
| 代理商： | PALLV22V10Z-25PI |
2
PALLV22V10 and PALLV22V10Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALLV22V10 is the low-voltage version of the PALCE22V10. It has all the architectural features
of the PALCE22V10.
The PALLV2210Z is the low-voltage, zero-power version of the PALCE22V10. It has all the
architectural features of the PALCE22V10. In addition, the PALLV22V10Z has zero standby power
and an unused product term disable feature.
The PALLV22V10 allows the systems engineer to implement a design on-chip by programming EE
cells to congure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modied during
prototyping or production.
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The PALLV22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output congurations; registered output or combinatorial I/O, active high or active low
(see Figure 2). The conguration choice is made according to the user’s design specication and
corresponding programming of the conguration bits S0 - S1. Multiplexer controls are connected
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it oats to VCC (1), selecting the “1” path.
The device is produced with a EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
customized pattern.
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
RESET
PRESET
CLK/I0
1
I1 - I11
11
8
1012
14
16
1614
12
10
8
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
PROGRAMMABLE
AND ARRAY
(44 x 132)
18956D-001
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PAT4556C0DBAB | 0 MHz - 10000 MHz RF/MICROWAVE FIXED ATTENUATOR |
| PBRC-2.00AR | |
| PBRC4.00HR50X000 | RSNTR 4.00MHZ 33PF 0.5% CER SMD-3.4X7.4 -40+85C T&R |
| PC-SO5 | 2 ELEMENT, 10000000 uH, GENERAL PURPOSE INDUCTOR |
| PC-SSO-23 | 2 ELEMENT, 8000000 uH, GENERAL PURPOSE INDUCTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALLV22V10Z25SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PALM-L1 | 制造商:Panduit Corp 功能描述:B-ID |
| PALM-L2 | 制造商:Panduit Corp 功能描述:B-ID |
| PALM-T1 | 制造商:Panduit Corp 功能描述:WIRE MARKER T1 PANDUIT |
| PALM-T2 | 制造商:Panduit Corp 功能描述:WIRE MARKER T2 PANDUIT |
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