參數(shù)資料
型號: PALLV16V8-10SC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述: EE PLD, 10 ns, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 5/22頁
文件大?。?/td> 425K
代理商: PALLV16V8-10SC
PALLV16V8-10 and PALLV16V8Z-20 Families
5
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written
in their most compact form (true or inverted), and the output can still be of the desired polarity.
It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1
of the AND/OR logic. The output is active high if SL1
x
which controls an exclusive-OR gate at the output
is 1 and active low if SL1
x
x
is 0.
Table 1. Macrocell Configuration
SG0
SG1
SL0
X
Cell
Configuration
Devices
Emulated
SG0
SG1
SL0
X
Cell
Configuration
Devices
Emulated
Device Uses Registers
Device Uses No Registers
0
1
0
Registered
Output
PAL16R8, 16R6,
16R4
1
0
0
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8, 12L6,
14L4, 16L2
0
1
1
Combinatorial
I/O
PAL16R6, 16R4
1
0
1
Input
PAL12H6, 14H4, 16H2, 12L6,
14L4, 16L2
1
1
1
Combinatorial
I/O
PAL16L8
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