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參數(shù)資料
| 型號(hào)： | PALLV16V8-10PC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| 中文描述： | EE PLD, 10 ns, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 425K |
| 代理商： | PALLV16V8-10PC |
PALLV16V8-10 and PALLV16V8Z-20 Families
19
POWER-UP RESET
The PALLV16V8 has been designed with the capability to reset during system power-up. Following
power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the
logic polarity. This feature provides extra flexibility to the designer and is especially valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V
CC
can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
N
The V
CC
rise must be monotonic.
N
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Min
Max
Unit
t
PR
Power-Up Reset Time
1000
ns
See Swtching Characteristics
t
S
Input or Feedback Setup Time
t
WL
Clock Wdth LOW
17713D-16
t
PR
t
WL
t
S
2.7 V
V
CC
Power
Registered
Output
Clock
Figure 3. Power-Up Reset Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALLV16V8-10SC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| PALLV16V8Z-20JI | 制造商: 功能描述: 制造商:undefined 功能描述: |
| PALLV16V8Z-20PI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:Simple E2PLD, Programmable Array Logic, 20 Pin, Plastic, DIP 制造商:Lattice Semiconductor Corporation 功能描述: |
| PALLV16V8Z-20SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| PALLV16V8Z-25JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
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