參數(shù)資料
型號(hào)： PALCE22V10H-20PI/4
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： 24-Pin EE CMOS (Zero Power) Versatile PAL Device
中文描述： EE PLD, 20 ns, PDIP24
封裝： 0.300 INCH, SKINNY, PLASTIC, DIP-24
文件頁(yè)數(shù)： 11/34頁(yè)
文件大小： 691K
代理商： PALCE22V10H-20PI/4
PALCE22V10H-10/15/20/25 (Ind)
19
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
5
pF
COUT
Output Capacitance
VOUT = 2.0 V
8
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-10
-15
-20
-25
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPD
Input or Feedback to Combinatorial Output
10
15
20
25
ns
tS
Setup Time from Input, Feedback or SP to Clock
7
10
12
15
ns
tH
Hold Time
0000
ns
tCO
Clock to Output
6
10
12
15
ns
tAR
Asynchronous Reset to Registered Output
13
20
25
ns
tARW
Asynchronous Reset Width
8
15
20
25
ns
tARR
Asynchronous Reset Recovery Time
8
10
20
25
ns
tSPR
Synchronous Preset Recovery Time
8
10
14
25
ns
tWL
Clock Width
LOW
4
8
10
13
ns
tWH
HIGH
4
8
10
13
ns
fMAX
Maximum
Frequency
(Note 2)
External Feedback
1/(tS + tCO)
83.3
50
41.6
33.3
MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 110
58.8
45.4
35.7
MHz
No Feedback
1/(tWH + tWL)
125
83.3
50
38.5
MHz
tEA
Input to Output Enable Using Product Term Control
10
15
20
25
ns
tER
Input to Output Disable Using Product Term Control
9
15
20
25
ns
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