參數(shù)資料
型號(hào)： PALCE20V8Q-25PI/4
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： EE CMOS 24-Pin Universal Programmable Array Logic
中文描述： EE PLD, 25 ns, PDIP24
封裝： 0.300 INCH, SKINNY, PLASTIC, DIP-24
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 479K
代理商： PALCE20V8Q-25PI/4
PALCE20V8H-15/25 Q-15/25 (Com’l)
13
USE
GAL
DEVICES
FOR
NEW
DESIGNS
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
5pF
COUT
Output Capacitance
VOUT = 2.0 V
8
pF
Parameter
Symbol
Parameter Description
-15
-25
Unit
Min
Max
Min
Max
tPD
Input or Feedback to Combinatorial Output
15
25
ns
tS
Setup Time from Input or Feedback to Clock
12
15
ns
tH
Hold Time
0
ns
tCO
Clock to Output
10
12
ns
tWL
Clock Width
LOW
8
12
ns
tWH
HIGH
8
12
ns
fMAX
Maximum
Frequency
(Note 2)
External Feedback
1/(tS+tCO)
45.5
37
MHz
Internal Feedback (fCNT)
1/(tS+tCF) (Note 3)
50
40
MHz
No Feedback
1/(tWH+tWL)
62.5
41.6
MHz
tPZX
OE to Output Enable
15
20
ns
tPXZ
OE to Output Disable
15
20
ns
tEA
Input to Output Enable Using Product Term Control
15
25
ns
tER
Input to Output Disable Using Product Term Control
15
25
ns
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