參數(shù)資料
型號(hào): PALCE20V8H-15PI/4
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: EE CMOS 24-Pin Universal Programmable Array Logic
中文描述: EE PLD, 15 ns, PDIP24
封裝: 0.300 INCH, SKINNY, PLASTIC, DIP-24
文件頁(yè)數(shù): 22/25頁(yè)
文件大?。?/td> 479K
代理商: PALCE20V8H-15PI/4
6
PALCE20V8 Family
USE
GAL
DEVICES
FOR
NEW
DESIGNS
D
Q
OE
CLK
a. Registered active Low
D
Q
OE
CLK
b. Registered active high
c. Combinatorial I/O active low
d. Combinatorial I/O active high
e. Combinatorial output active low
VCC
f. Combinatorial output active high
VCC
Adjacent I/O Pin
g. Dedicated input
Notes:
1. Feedback is not available on pins 18 (21) and 19 (23) in
the combinatorial output mode.
2. This macrocell conguration is not available on pins
18 (21) and 19 (23).
Note 1
Note 2
16491E
Figure 2. Macrocell Congurations
相關(guān)PDF資料
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