參數(shù)資料
型號(hào)： PALC22V10-25JC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Flash-erasable Reprogrammable CMOS PAL Device
中文描述： OT PLD, 25 ns, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 367K
代理商： PALC22V10-25JC
PALCE22V10
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 6 of 13
t
S1
t
S2
Input or Feedback Set-Up Time
Synchronous Preset Set-Up
Time
Input Hold Time
External Clock Period (t
CO
+ t
S
)
Clock Width HIGH
[6]
Clock Width LOW
[6]
External Maximum
Frequency (1/(t
CO
+ t
S
))
[11]
Data Path Maximum Frequency
(1/(t
WH
+ t
WL
))
[6, 12]
Internal Feedback Maximum
Frequency (1/(t
CF
+ t
S
))
[6,13]
Register Clock to
Feedback Input
[6,14]
Asynchronous Reset Width
Asynchronous Reset
Recovery Time
Asynchronous Reset to
Registered Output Delay
Synchronous Preset
Recovery Time
Power-up Reset Time
[6,15]
Military and Industrial Switching Characteristics PALCE22V10
[2, 7]
3
4
5
6
6
7
10
10
15
15
ns
ns
t
H
t
P
t
WH
t
WL
f
MAX1
0
7
0
10
3
3
100
0
12
3
3
76.9
0
20
6
6
55.5
0
30
13
13
33.3
ns
ns
ns
ns
MHz
2.5
2.5
143
f
MAX2
200
166
142
83.3
35.7
MHz
f
MAX3
181
133
111
68.9
38.5
MHz
t
CF
2.5
2.5
3
4.5
13
ns
t
AW
t
AR
8
4
8
5
10
6
15
10
25
25
ns
ns
t
AP
7.5
12
13
20
25
ns
t
SPR
4
6
8
10
15
ns
t
PR
1
1
1
1
1
μ
s
Parameter
Description
22V10-10
Min.
3
22V10-15
Min.
3
22V10-25
Min.
3
Unit
ns
Max.
10
Max.
15
Max.
25
t
PD
Input to Output
Propagation Delay
[8]
Input to Output Enable Delay
[9]
Input to Output Disable Delay
[10]
Clock to Output Delay
[8]
Input or Feedback Set-up Time
Synchronous Preset Set-up Time
Input Hold Time
External Clock Period (t
CO
+ t
S
)
Clock Width HIGH
[6]
Clock Width LOW
[6]
External Maximum Frequency
(1/(t
CO
+ t
S
))
[11]
Data Path Maximum Frequency
(1/(t
WH
+ t
WL
))
[6, 12 ]
t
EA
t
ER
t
CO
t
S1
t
S2
t
H
t
P
t
WH
t
WL
f
MAX1
10
10
7
15
15
8
25
25
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
2
6
7
0
12
3
3
76.9
2
2
10
10
0
20
6
6
50.0
18
18
0
33
14
14
30.3
f
MAX2
142
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12.This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13.This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14.This parameter is calculated from the clock period at f
internal (1/f
) as measured (see Note above) minus t
.
15.The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in V
CC
must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
Commercial Switching Characteristics PALCE22V10
(continued)
[2, 7]
Parameter
Description
22V10-5
Min.
22V10-7
Min.
22V10-10
Min.
22V10-15
Min.
22V10-25
Min.
Unit
Max.
Max.
Max.
Max.
Max.
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PALC22V10-25PC 功能描述:IC SPLD 10MACROCELL 25NS 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - PLD（可編程邏輯器件） 系列:- 標(biāo)準(zhǔn)包裝:46 系列:- 可編程類型:PAL FLASH 宏單元數(shù):8 輸入電壓:5V 速度:15ns 安裝類型:表面貼裝 封裝/外殼:20-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:20-PLCC（9x9） 包裝:管件 其它名稱:428-1277
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