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參數(shù)資料
| 型號(hào)： | PACVGA201Q |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | VGA PORT COMPANION CIRCUIT |
| 中文描述： | VGA端口伴侶電路 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大小： | 129K |
| 代理商： | PACVGA201Q |
2000 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
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CALIFORNIA MICRO DEVICES
PACVGA201
VGA PORT COMPANION CIRCUIT
Features
7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
Three power supplies for design flexibility
Compact 16-pin QSOP package
C0651299
PAC VGA201 is a trademark of California Micro Devices Corp.
Pin Diagram
Schematic Diagram
Product Description
The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low
voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.
An internal diode (D1, in schematic below) is provided such that V
is derived from V
. (V
does not require an external
power supply input.) In applications where V
CC3
may be powered down, diode D1 blocks any DC current path from the
DDC_OUT pins back to the powered down V
CC3
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
CC3
.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the V
CC3
supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
16-PIN QSOP PACKAGE
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相關(guān)代理商/技術(shù)參數(shù) |
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| PACVGA201QR | 功能描述:ESD 抑制器 ESD Net VGA Port Companion Circuit RoHS:否 制造商:STMicroelectronics 通道:8 Channels 擊穿電壓:8 V 電容:45 pF 端接類型:SMD/SMT 封裝 / 箱體:uQFN-16 功率耗散 Pd: 工作溫度范圍:- 40 C to + 85 C |
| PACVGA203 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA Port Companion Circuit |
| PACVGA203Q | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA Port Companion Circuit |
| PACVGA203QR | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA Port Companion Circuit |
| PACZIG1284 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PActive? IEEE 1284 Parallel Port ESD/EMI/Termination Network. |
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