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參數(shù)資料
| 型號： | PACVGA100 |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | VGA Port ESD Protection and Termination Network |
| 中文描述： | VGA端口ESD保護和終端網(wǎng)絡 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 74K |
| 代理商： | PACVGA100 |
2002 California Micro Devices Corp. All rights reserved.
4
215 Topaz Street, Milpitas, California 95035
L
Tel: (408) 263-3214
L
Fax: (408) 263-7846
L
www.calmicro.com
02/14/02
PACVGA100/101
Specifications (cont’d)
Note 1: All parameters specified at T
A
=25°C unless otherwise noted.
Note 2: These parameters guaranteed by design and characterization.
Note 3: From I/O pins to V
P
or V
N
only; V
P
bypassed to V
N
with 0.2
μ
F ceramic capacitor.
Note 4: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
= 100pF, R
Discharge
= 1.5K
,
V
P
= 5.0V, V
N
grounded.
Note 5: Standard IEC 61000-4-2 with C
Discharge
= 150pF, R
Discharge
= 330
, V
P
= 5.0V, V
N
grounded.
Note 6: These pins are not directly connected to the VGA connector and therefore are not subject to direct ESD strikes.
ELECTRICAL OPERATING CHARACTERISTICS
1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TOL
R
Resistor Absolute Tolerance
R/G/B Termination Resistor (R1)
Series Termination Resistor (R2)
DDC Pull-up Resistor (R3)
+5
+5
+10
%
%
%
TCR
Temperature Coefficient of Resistance (TCR)
+200
ppm/°C
V
F
Diode Forward Voltage
I
F
= 20mA
0.65
0.95
V
V
RB
Diode Reverse Breakdown Voltage
Top Diode (Cathode connected to V
CC
)
Bottom Diode (Anode connected to V
SS
)
17.0
25.0
V
V
I
LEAK
Channel Leakage Current
+0.1
+1.0
μ
A
C
IN
Channel Input Capacitance at pins 2, 3, 5, 6, 10, 12 &
15
@ 1 MHz,
V
P
=5V, V
N
=0V,
V
IN
=2.5V; Note
2 applies
4.5
6
pF
V
ESD
ESD Protection
1) Peak Discharge Voltage at pins 2, 3, 5, 6 10, 12
& 15,
in system
a) Human Body Model, MIL-STD-883, Method
3015
b) Contact discharge per IEC 61000-4-2
2) Peak Discharge Voltage at pins 7, 9, 11 & 14
a) Human Body Model, MIL-STD-883, Method
3015
Note 3
Notes 2,4
Notes 2,5
Note 6
Notes 2,4
+
15
+
8
+
4
kV
kV
kV
V
CP
Channel Clamp Voltage at pins 2, 3, 5, 6, 10, 12 & 15
Positive Transients
Negative Transients
@15kV ESD
HBM; Notes 2 &
4
V
P
+ 13.0
V
N
- 13.0
V
V
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| PACVGA101 | VGA Port ESD Protection and Termination Network |
| PACVGA105 | VGA Port Companion Circuit |
| PACVGA105Q | VGA Port Companion Circuit |
| PACVGA105QR | VGA Port Companion Circuit |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PACVGA-100 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA PROTECTION AND TERMINATION NETWORK |
| PACVGA-100R | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA PROTECTION AND TERMINATION NETWORK |
| PACVGA-100T | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA PROTECTION AND TERMINATION NETWORK |
| PACVGA101 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA Port ESD Protection and Termination Network |
| PACVGA-101 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:VGA PROTECTION AND TERMINATION NETWORK |
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