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參數(shù)資料
| 型號： | PACDN007Q |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | 18 CHANNEL ESD PROTECTION ARRAY |
| 中文描述： | 18通道ESD保護(hù)陣列 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大小： | 131K |
| 代理商： | PACDN007Q |
1999 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
11/98
3
CALIFORNIA MICRO DEVICES
PAC DN007
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies
exhibit a much higher output impedance to fast transient current spikes. In the V
Z
equation above, the V
Supply
term, in
reality, is given by (V
DC
+ I
esd
x R
out
), where V
DC
and R
out
are the nominal supply DC output voltage and effective output
impedance of the power supply respectively. As an example, a R
out
of 1 ohm would result in a 10V increment in V
Z
for a
peak I
esd
of 10A.
To mitigate these effects, a high frequency bypass capacitor should be connected between the V
P
pin of the ESD Protection
Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge
transferred by the ESD pulse with minimal change in V
P
. Typically a value in the 0.1 μF to 0.2 μF range is adequate for
IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be
increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply
voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the
Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray
series inductance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PACDN009 | 5 Channel ESD Protection Array |
| PACDN009M | 5 Channel ESD Protection Array |
| PACDN009MR | 5 Channel ESD Protection Array |
| PACDN010 | P/ACTIVE SCHOTTKY DIODE MEMORY BUS TERMINATOR |
| PACDN010QR | P/ACTIVE SCHOTTKY DIODE MEMORY BUS TERMINATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PACDN009 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:5 Channel ESD Protection Array |
| PACDN009M | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:5 Channel ESD Protection Array |
| PACDN009MR | 功能描述:ESD 抑制器 5-ch ESD Protection RoHS:否 制造商:STMicroelectronics 通道:8 Channels 擊穿電壓:8 V 電容:45 pF 端接類型:SMD/SMT 封裝 / 箱體:uQFN-16 功率耗散 Pd: 工作溫度范圍:- 40 C to + 85 C |
| PACDN010 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:P/ACTIVE SCHOTTKY DIODE MEMORY BUS TERMINATOR |
| PACDN010Q/T | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:APPLICATION SPECIFIC DIODE ARRAY|SO |
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