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參數(shù)資料
| 型號： | PA7540J-15 |
| 英文描述： | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| 中文描述： | PA7540果皮陣列？電可擦除可編程邏輯陣列 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 239K |
| 代理商： | PA7540J-15 |
2
04-02-051B
Inside the Logic Array
The heart of the PEEL Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7540 PEEL Array, 42 inputs are
available into the array from the I/O cells and input/global-
clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7540 PEEL Arrays contains 84 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
From
IO Cells
(IOC) and
I/CLKs
From
Logic
Control
Cells
(LCC)
To
Global
Cells
42 Array Inputs
84 Product Terms
To
Logic Control
Cells
(LCC)
84 Sum Terms
PA7540 Logic Array
08-14-003A
Figure 3 PA7540 Logic Array
True Product-Term Sharing
The PEEL logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can be
used for clocks, resets, presets and output enables instead of
just simple product-term control.
The PEEL logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
A
B
C
D
REG
D,T,J
K
R
P
Q
MUX
System Clock
Preset
Reset
On/Off
RegType
From Global Cell
MUX
MUX
To
Array
To
I/O
Cell
From
Array
08-14-004A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
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PDF描述 |
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| PA7540 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540P-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540PI-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540S-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540SI-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PA7540J-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JI-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JI-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 2 Input 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JN-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JN-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 2 Input 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
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