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參數(shù)資料
| 型號： | PA7024J-20 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Electrically Erasable Logic Array |
| 中文描述： | 電可擦除可編程邏輯陣列 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 427K |
| 代理商： | PA7024J-20 |
4 of 6
PA7024
Table 1. A.C. Electrical Characteristics Sequential over the operating range
Symbol
Parameter
6,12
-15
-20
I-25
Unit
Min
Max
Min
Max
Min
Max
t
SCI
Internal set-up to system clock
8
- LCC
14
(t
AL
+ t
SK
+ t
LC
- t
CK
)
6
9
15
ns
t
SCX
Input
16
(EXT.) set-up to system clock, - LCC (t
IA +
t
SCI)
8
11
17
ns
t
COI
System-clock to Array Int. - LCC/IOC/INC
14
(t
CK
+t
LC
)
8
8
8
ns
t
COX
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
12
13
13
ns
t
HX
Input hold time from system clock - LCC
0
0
0
ns
t
SK
LCC Input set-up to async. clock
13
- LCC
3
3
4
ns
t
AK
Clock at LCC or IOC - LCC output
1
1
1
ns
t
HK
LCC input hold time from system clock - LCC
4
4
4
ns
t
SI
Input set-up to system clock - IOC/INC
14
(t
SK
- t
CK
)
0
0
0
ns
t
HI
Input hold time from system clock - IOC/INC
14
(t
SK
- t
CK
)
4
4
4/3
ns
t
PK
Array input to IOC PCLK clock
6
7
9
ns
t
SPI
Input set-up to PCLK clock
18
- IOC/INC (t
SK
-t
PK
-t
IA
)
16
0
0
0
ns
t
HPI
Input hold from PCLK clock
18
- IOC/INC (t
PK
+t
IA
-t
SK
)
16
5
6
7
ns
t
CK
System-clock delay to LCC/IOCINC
7
7
7
ns
t
CW
System-clock low or high pulse width
7
7
8
ns
f
MAX
1
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
71.4
58.8
43.5
MHz
f
MAX
2
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
62.5
52.6
40.0
MHz
f
MAX
3
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
55.5
45.5
35.7
MHz
f
MAX
4
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
50.0
41.6
33.3
MHz
f
TGL
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
9
71.4
71.4
62.5
MHz
t
PR
LCC presents/reset to LCC output
1
1
2
ns
t
ST
Input to Global Cell present/reset (
tIA
+ t
AL
+ t
PR
)
12
15
20
ns
t
AW
Asynch. preset/reset pulse width
8
8
8
ns
t
RT
Input to LCC Reg-Type (RT)
6
8
10
ns
t
RTV
LCC Reg-Type to LCC output register change
1
1
2
ns
t
RTC
Input to Global Cell register-type change (t
RT
+ t
RTV
)
7
9
12
ns
t
RW
Asynch. Reg-Type pulse width
10
10
10
ns
t
RESET
Power-on reset time for registers in clear state
2
5
5
5
μs
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