參數(shù)資料
型號： PA28F800CV-T80
廠商： Intel Corp.
英文描述： 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
中文描述： 2兆位SmartVoltage啟動塊閃存系列
文件頁數(shù)： 48/55頁
文件大?。?/td> 638K
代理商： PA28F800CV-T80
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
48
SEE NEW DESIGN RECOMMENDATIONS
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC
= 5.0 V, T = +25
°C. These currents are valid for all
product versions (packages and speeds).
2. I
CCES
is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I
CCES
and I
CCR
.
3. Block erases and word/byte programs inhibited when V
PP
= V
PPLK
, and not guaranteed in the range between V
PPH
1 and
V
PPLK
.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I
CCR
to less than 1 mA typical, in static operation.
6. CMOS Inputs are either V
CC
± 0.2 V or GND ± 0.2 V. TTL Inputs are either V
IL
or V
IH
.
7. For the 28F002B address pin A
10
follows the C
OUT
capacitance numbers.
8. For all BV/CV parts, V
LKO
= 2.0 V for 3.3 V and 5.0 V operations.
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
0530_12
NOTE:
AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 19. 3.3 V Input Range and Measurement Points
TEST POINTS
INPUT
OUTPUT
2.0
0.8
0.8
2.0
2.4
0.45
0530_13
NOTE:
AC test inputs are driven at V
(2.4 V
) for a logic “1” and V
(0.45 V
) for a logic “0.” Input timing begins at V
IH
(2.0 V
TTL
)
and V
IL
(0.8 V
TTL
). Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) < 10 ns.
Figure 20. 5 V Input Range and Measurement Points
C
L
OUT
V
CC
DEVICE
UNDER
TEST
R
1
R
2
0530_14
NOTE:
See table for component values.
Figure 21. Test Configuration
Test Configuration Component Values
Test Configuration
C
L
(pF)
R
1
(
) R
2
(
)
3.3 V Standard Test
50
990
770
5 V Standard Test
100
580
390
NOTE:
C
L
includes jig capacitance.
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