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| 型號： | PA28F200BX-B60 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | ACTUATOR, SWITCH, ROUND, LATCH; Approval Bodies:BEAB, VDE, UL, CSA; Diameter, external:29mm; IP rating:65; Operations, mechanical No. of:100000; Temp, op. max:85(degree C); Temp, op. min:-20(degree C) RoHS Compliant: Yes |
| 中文描述： | 128K X 16 FLASH 12V PROM, 60 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 41/48頁 |
| 文件大小： | 562K |
| 代理商： | PA28F200BX-B60 |
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28F200BX-T/B, 28F002BX-T/B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR WE
Y
-CONTROLLED WRITE OPERATIONS
(1)
Versions
(4)
T28F200BX-80
(9)
T28F002BX-80
(9)
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
80
ns
t
PHWL
t
PS
RP
Y
High Recovery to
WE
Y
Going Low
220
ns
t
ELWL
t
CS
CE
Y
Setup to WE
Y
Going Low
0
ns
t
PHHWH
t
PHS
RP
Y
V
HH
Setup to WE
Y
Going High
V
PP
Setup to WE
Y
Going High
Address Setup to WE
Y
Going High
6, 8
100
ns
t
VPWH
t
VPS
5, 8
100
ns
t
AVWH
t
AS
3
60
ns
t
DVWH
t
DS
Data Setup to WE
Y
Going High
4
60
ns
t
WLWH
t
WP
WE
Y
Pulse Width
60
ns
t
WHDX
t
DH
Data Hold from WE
Y
High
4
0
ns
t
WHAX
t
AH
Address Hold from WE
Y
High
3
10
ns
t
WHEH
t
CH
CE
Y
Hold from WE
Y
High
10
ns
t
WHWL
t
WPH
WE
Y
Pulse Width High
20
ns
t
WHQV1
Duration of Word/Byte
Write Operation
2, 5
7
m
s
t
WHQV2
Duration of Erase Operation (Boot)
2, 5, 6
0.4
s
t
WHQV3
Duration of Erase
Operation (Parameter)
2, 5
0.4
s
t
WHQV4
Duration of Erase Operation (Main)
2, 5, 6
0.7
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD
RP
Y
V
HH
Hold from Valid SRD
5, 8
0
ns
t
QVPH
t
PHH
6, 8
0
ns
t
PHBR
Boot-Block Relock Delay
7, 8
100
ns
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-
nally which includes verify and margining operations.
3. Refer to command definition table for valid A
IN
.
4. Refer to command definition table for valid D
IN
.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7
e
1).
6. For Boot Block Program/Erase, RP
Y
should be held at V
HH
until operation completes successfully.
7. Time t
PHBR
is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
9. See Standard Test Configuration.
41
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