參數資料
型號: PA28F200BX-B120
廠商: INTEL CORP
元件分類: PROM
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 128K X 16 FLASH 12V PROM, 120 ns, PDSO44
封裝: 1.110 X 0.525 INCH, PLASTIC, SOP-44
文件頁數: 48/48頁
文件大?。?/td> 562K
代理商: PA28F200BX-B120
28F200BX-T/B, 28F002BX-T/B
Revision History
Number
Description
-002
Removed
b
70 speed bin
Integrated
b
70 characteristics into
b
60 speed bin
Added Extended Temperature characteristics
Modified BYTE
Y
Timing Diagram
Improved t
PHQV
, RP
Y
High to Output Delay and t
PHEL
, RP
Y
High Recovery to CE
Y
going low
specifications
-003
PWD changed to RP
Y
for JEDEC standardization compatibility.
Combined V
CC
Read current for 28F200BX Word-wide mode and Byte-wide mode, and
28F002BX Byte-wide mode in DC Characteristics tables.
Change I
PPS
current spec from
g
10
m
A to
g
15
m
A in DC Characteristics tables.
Improved I
CCR
and I
CCW
in DC Characteristics: Extended Temperature Operation table.
Improved t
AVAV
, t
AVQV
, t
ELQV
, t
GLQV
, t
EHQZ
, t
GHQZ
, t
FHQV
and t
FLQZ
specifications for
Extended Temperature Operations AC CharacteristicsDRead and Write Operations.
-004
Added specifications for 120 ns access time product version; 28F200BX-120 and
28F002BX-120.
Included permanent change on write timing parameters for -80 ns product versions. Write
pulse width (t
WP
and t
CP
) increases from 50 ns to 60 ns. Write pulse width high (t
WPH
and
t
CPH
) decreases from 30 ns to 20 ns. Total write cycle time (t
WC
) remains unchanged.
Added I
CCR
test condition note for typical frequency value in DC characteristics table.
Added I
OH
CMOS specification.
Added 28F400BX interface to Intel386
TM
EX Embedded Processor block diagram.
Added description of how to upgrade to SmartVoltage Boot Block products.
-005
Added references to input rise/fall times.
48
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