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Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.07
92
Freescale Semiconductor
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
L
PL7
(TXD7)
O
Serial Communication Interface 7 transmit pin
GPIO
GPIO
I/O General-purpose I/O
PL6
(RXD7)
I
Serial Communication Interface 7 receive pin
GPIO
I/O General-purpose I/O
PL5
(TXD6)
O
Serial Communication Interface 6 transmit pin
GPIO
I/O General-purpose I/O
PL4
(RXD6)
I
Serial Communication Interface 6 receive pin
GPIO
I/O General-purpose I/O
PL3
(TXD5)
O
Serial Communication Interface 5 transmit pin
GPIO
I/O General-purpose I/O
PL2
(RXD5)
I
Serial Communication Interface 5 receive pin
GPIO
I/O General-purpose I/O
PL1
(TXD4)
O
Serial Communication Interface 4 transmit pin
GPIO
I/O General-purpose I/O
PL0
(RXD4)
I
Serial Communication Interface 4 receive pin
GPIO
I/O General-purpose I/O
F
PF7
(TXD3)
O
Serial Communication Interface 3 transmit pin
GPIO
GPIO
I/O General-purpose I/O
PF6
(RXD3)
I
Serial Communication Interface 3 receive pin
GPIO
I/O General-purpose I/O
PF5
(SCL0)
O
Inter Integrated Circuit 0 serial clock line
GPIO
I/O General-purpose I/O
PF4
(SDA0)
I/O Inter Integrated Circuit 0 serial data line
GPIO
I/O General-purpose I/O
PF3
(CS3)
O
Chip select 3
GPIO
I/O General-purpose I/O
PF2
(CS2)
O
Chip select 2
GPIO
I/O General-purpose I/O
PF1
(CS1)
O
Chip select 1
GPIO
I/O General-purpose I/O
PF0
(CS0)
O
Chip select 0
GPIO
I/O General-purpose I/O
1
Signals in brackets denote alternative module routing pins.
2
Function active when RESET asserted.
3
Only available in emulation modes or in Special Test Mode with IVIS on.
4
Refer to S12X_EBI section.
Port
Pin Name
Pin Function
& Priority
1
I/O
Description
Pin Function
after Reset