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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
1137
Figure 27-28. Example Program Command Flow
Write: Flash Address
and program Data
Write: FCMD register
Program Command 0x20
Write: FSTAT register
Clear CBEIF 0x80
1.
2.
3.
Clear ACCERR/PVIOL 0x30
Write: FSTAT register
yes
no
Access Error and
Protection Violation
Check
no
Bit Polling for
Buffer Empty
Check
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
CBEIF
Set
Next
Flash
Block
no
yes
Address, Data,
Command
Buffer Empty Check
CBEIF
Set
ACCERR/
PVIOL
Set
EXIT
by 128K
Decrement Global Address
Write: FCLKDIV register
Read: FCLKDIV register
yes
no
Clock Register
Written
Check
FDIVLD
Set
NOTE: FCLKDIV needs to
be set once after each reset.
Simultaneous
Multiple Flash Block
Decision
no
yes
Sequential
Programming
Decision
Next
Word
no
Bit Polling for
Command Completion
Check
Read: FSTAT register
yes
CCIF
Set