參數(shù)資料
型號(hào): P89V660FA,512
廠商: NXP Semiconductors
文件頁數(shù): 21/90頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 1,300
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2432-5
935280828512
P89V660FA
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
28 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.4.4 I2C-bus status register
This is a read-only register. It contains the status code of the I2C-bus interface. The least
three bits are always 0. There are 26 possible status codes. When the code is F8H, there
is no relevant information available and SI bit is not set. All other 25 status codes
correspond to defined I2C-bus states. When any of these states entered, the SI bit will be
set. Refer to Table 22 to Table 25 for details.
6.4.5 I2C-bus operation modes
6.4.5.1
Master transmitter mode
In this mode data is transmitted from master to slave. Before the Master Transmitter mode
can be entered, S1CON must be initialized as follows:
CR2:0 define the bit rate (See Table 17). ENS1 must be set to 1 to enable the I2C-bus
function. If the AA bit is 0, it will not acknowledge its own slave address or the general call
address in the event of another device becoming master of the bus and it can not enter
slave mode. STA, STO, and SI bits must be cleared to 0.
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a
write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
101
100
200
50
100
60
120
110
200
400
100
200
30
60
111
0.49 < 62.5
0.98 < 50.0
0.24 < 62.5
0.49 < 62.5
48 x (Timer 1
reload)
96 x (Timer 1
reload)
Table 17.
I2C-bus clock rates …continued
CR2:0
Bit frequency at fosc
6-clock mode
12-clock mode
fosc divided by
6 MHz
12 MHZ
6 MHz
12 MHz
6X
12X
Table 18.
I2C-bus status register (S1STA - address D9H) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SC.4
SC.3
SC.2
SC.1
SC.0
0
Reset
0000
Table 19.
I2C-bus status register (S1STA - address D9H) bit description
Bit
Symbol
Description
7:3 SC[4:0]
I2C-bus Status code.
2:0 -
Reserved, are always set to 0.
Table 20.
I2C-bus control register (S1CON - address D8H)
Bit
7
6
5
4
3
2
1
0
Symbol
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Value
bit rate
1
0
x
bit rate
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