參數(shù)資料
型號: P89V51RC2BN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40
文件頁數(shù): 61/77頁
文件大?。?/td> 350K
代理商: P89V51RC2BN
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
61 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.12.2
Clock doubling option
By default, the device runs at 12 clocks per machine cycle (x1 mode). The device has
a clock doubling option to speed up to 6 clocks per machine cycle (please see
Table 60
). Clock double mode can be enabled either by an external programmer or
using IAP. When set, the EDC bit in FST register will indicate 6 clock mode.
The clock double mode is only for doubling the internal system clock and the internal
flash memory, i.e. EA = 1. To access the external memory and the peripheral devices,
careful consideration must be taken. Also note that the crystal output (XTAL2) will not
be doubled.
Using the on-chip oscillator
External clock drive
Fig 28. Oscillator characteristics.
002aaa543
XTAL2
XTAL1
VSS
C1
C2
002aaa546
XTAL2
NC
XTAL1
external
oscillator
signal
VSS
Table 60:
Device
Clock doubling features
Standard mode (x1)
Clocks per
machine cycle
Clock double mode (x2)
Clocks per
machine cycle
Max. external
clockfrequency
(MHz)
40
Max. external
clockfrequency
(MHz)
20
P89V51RD2
12
6
Table 61:
Not Bit addressable; Reset value: xxxxx0xxB
Bit
7
Symbol
-
FST - Flash status register (address B6) bit allocation
6
5
-
4
-
3
2
-
1
-
0
-
SB
EDC
Table 62:
Bit
7
6
5 to 4
3
2 to 0
FST - Flash status register (address B6) bit description
Symbol
Description
-
Reserved for future use. Should be set to ‘0’ by user programs.
SB
Security bit.
-
Reserved for future use. Should be set to ‘0’ by user programs.
EDC
Enable double clock.
-
Reserved for future use. Should be set to ‘0’ by user programs.
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