參數(shù)資料
型號(hào): P89V51RB2BBC
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, TQFP-44
文件頁(yè)數(shù): 38/77頁(yè)
文件大?。?/td> 350K
代理商: P89V51RB2BBC
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
38 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.5.1
Mode 0
Serial data enters and exits through RxD and TxD outputs the shift clock. Only 8 bits
are transmitted or received, LSB first. The baud rate is fixed at
1
6
of the CPU clock
frequency. UART configured to operate in this mode outputs serial clock on TxD line
no matter whether it sends or receives data on RxD line.
7.5.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0),
8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer
1
2
overflow rate.
7.5.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When
data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or
(e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received,
the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit
is ignored. The baud rate is programmable to either
1
16
or
1
32
of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.5.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact,
Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer
1
2
overflow rate.
Table 25:
Bit addressable; Reset value: 00H
Bit
7
Symbol
SM0/FE
SCON - Serial port control register (address 98H) bit allocation
6
5
4
3
2
1
0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 26:
Bit
7
SCON - Serial port control register (address 98H) bit description
Symbol
Description
SM0/FE
The usage of this bit is determined by SMOD0 in the PCON
register. If SMOD0 = 0, this bit is SM0, which with SM1, defines
the serial port mode. If SMOD0 = 1, this bit is FE (Framing Error).
FE is set by the receiver when an invalid stop bit is detected. Once
set, this bit cannot be cleared by valid frames but can only be
cleared by software. (Note: It is recommended to set up UART
mode bits SM0 and SM1 before setting SMOD0 to ‘1’.)
SM1
With SM0, defines the serial port mode (see
Table 27
below).
SM2
Enables the multiprocessor communication feature in Modes 2 and
3. In Mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if
the received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI
will not be activated if a valid stop bit was not received. In Mode 0,
SM2 should be ‘0’.
REN
Enables serial reception. Set by software to enable reception.
Clear by software to disable reception.
6
5
4
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