參數(shù)資料
型號: P89LV51RD2
廠商: NXP Semiconductors N.V.
英文描述: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
中文描述: 8位80C51的3 V低功耗64 kB閃存1 KB RAM內(nèi)存控制器
文件頁數(shù): 17/77頁
文件大小: 349K
代理商: P89LV51RD2
Philips Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 04 — 02 December 2004
17 of 77
9397 750 14342
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2. The higher 128 bytes of RAM (80H to FFH) are indirectly addressable.
3. The special function registers (80H to FFH) are directly addressable only.
4. The expanded RAM of 768 bytes (00H to 2FFH) is indirectly addressable by the
move external instruction (MOVX) and clearing the EXTRAM bit. (See ‘Auxiliary
Register (AUXR) in
Section 6 “Special function registers” on page 10
)
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must
be accessed indirectly. The RAM and SFRs space are physically separate even
though they have the same addresses.
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU
determines whether to access the SFRs or RAM by the type of instruction given. If it
is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the
examples below.
Indirect Access:
MOV@R0, #data; R0 contains 90H
Register R0 points to 90H which is located in the upper address range. Data in
‘#data’ is written to RAM location 90H rather than port 1.
Direct Access:
MOV90H, #data; write data to P1
Data in ‘#data’ is written to port 1. Instructions that write directly to the address write
to the SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX
instructions must be used. The extra 768 bytes of memory is physically located on the
chip and logically occupies the first 768 bytes of external memory (addresses 000H to
2FFH).
Table 7:
Not bit addressable; Reset value 00H
Bit
7
Symbol
-
AUXR - Auxiliary register (address 8EH) bit allocation
6
-
5
-
4
-
3
-
2
-
1
0
EXTRAM
AO
Table 8:
Bit
7 to 2
1
AUXR - Auxiliary register (address 8EH) bit description
Symbol
Description
-
Reserved for future use. Should be set to ‘0’ by user programs.
EXTRAM
Internal/External RAM access using MOVX @Ri/@DPTR.
When ‘0’, core attempts to access internal XRAM with address
specified in MOVX instruction. If address supplied with this
instruction exceeds on-chip available XRAM, off-chip XRAM is
going to be selected and accessed.
When ‘1’, every MOVX @Ri/@DPTR instruction targets external
data memory by default.
AO
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
1
2
the oscillator frequency. In case of AO = 1, ALE
is active only during a MOVX or MOVC.
0
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P89LV51RD2BN 功能描述:8位微控制器 -MCU 3V 64K/1K FL 12/6 CLK ISP/IAP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT