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參數(shù)資料
| 型號： | P89LPC972FN,129 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 18/66頁 |
| 文件大小： | 0K |
| 描述： | MCU 80C51 8KB FLASH 20DIP |
| 標準包裝： | 18 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 其它名稱： | 568-8749-5 P89LPC972FN,129-ND |
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P89LPC97X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 8 June 2010
25 of 66
NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
7.16 I/O ports
The P89LPC970/971/972 has four I/O ports: Port 0, Port 1 and Port 3. Ports 0, 1 are 8-bit
ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the
clock and reset options chosen, as shown in Table 7.
7.16.1 Port configurations
All but three I/O port pins on the P89LPC970/971/972 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
1. P1.5/RST can only be an input and cannot be configured.
2. P1.2/SCL/T0 and P1.3/INT0/SDA/T4 may only be configured to be either input-only or
open-drain.
7.16.1.1
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.16.1.2
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
Table 7.
Number of I/O pins available
Clock source
Reset option
Number of I/O
pins (20-pin
package)
On-chip oscillator or watchdog
oscillator
no external reset (except during
power-up)
18
external RST pin supported
17
External clock input
no external reset (except during
power-up)
17
external RST pin supported
16
Low/medium/high speed
oscillator (external crystal or
resonator)
no external reset (except during
power-up)
16
external RST pin supported
15
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