參數(shù)資料
型號: P89LPC952FA,512
廠商: NXP Semiconductors
文件頁數(shù): 22/69頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 26
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1016-ND - BOARD FOR P89LPC952FA 44-PLCC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
OM10075-ND - EVAL BOARD FOR LPC952
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2253-5
935280148512
P89LPC952FA
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
29 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.13 I/O ports
The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5.
Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O
pins available depends upon the clock and reset options and package chosen, as shown
[1]
Required for operation above 12 MHz.
7.13.1 Port congurations
All but three I/O port pins on the P89LPC952/954 may be congured by software to one of
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two conguration registers for each port
select the output type for each port pin.
1. P1.5/RST can only be an input and cannot be congured.
2. P1.2/T0/SCL and P1.3/INT0/SDA may only be congured to be either input-only or
open-drain.
7.13.1.1
Quasi-bidirectional output conguration
Quasi-bidirectional output type can be used as both an input and output without the need
to recongure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current owing from the pin to VDD,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
7.13.1.2
Open-drain output conguration
The open-drain output conguration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port congured in this manner must have an external pull-up, typically a resistor
tied to VDD.
Table 7.
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(48-pin package)
Number of I/O pins
(44-pin package)
On-chip oscillator or watchdog
oscillator
No external reset (except during power-up)
42
40
External RST pin supported
41
39
External clock input
No external reset (except during power-up)
41
39
External RST pin supported[1]
40
38
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during power-up)
40
38
External RST pin supported[1]
39
37
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