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  • 參數(shù)資料
    型號(hào): P89LPC936FDH
    廠商: NXP Semiconductors N.V.
    元件分類: 8位微控制器
    英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs
    封裝: P89LPC933FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC933HDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
    文件頁(yè)數(shù): 20/77頁(yè)
    文件大?。?/td> 537K
    代理商: P89LPC936FDH
    P89LPC933_934_935_936
    All information provided in this document is subject to legal disclaimers.
    NXP B.V. 2011. All rights reserved.
    Product data sheet
    Rev. 8 — 12 January 2011
    27 of 77
    NXP Semiconductors
    P89LPC933/934/935/936
    8-bit microcontroller with accelerated two-clock 80C51 core
    8.7 CCLK wake-up delay
    The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it
    stabilizes depending on the clock source used. If the clock source is any of the three
    crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles
    plus 60
    μsto100 μs. If the clock source is either the internal RC oscillator, watchdog
    oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60
    μs to 100 μs.
    8.8 CCLK modification: DIVM register
    The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
    register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
    CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
    retain the ability to respond to events that would not exit Idle mode by executing its normal
    program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
    where Power-down mode would otherwise be used. The value of DIVM may be changed
    by the program at any time without interrupting code execution.
    8.9 Low power select
    The P89LPC933/934/935/936 is designed to run at 18 MHz (CCLK) maximum. However,
    if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower
    the power consumption further. On any reset, CLKLP is logic 0 allowing highest
    performance access. This bit can then be set in software if CCLK is running at 8 MHz or
    slower.
    8.10 Memory organization
    The various P89LPC933/934/935/936 memory spaces are as follows:
    DATA
    128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
    addressing, using instructions other than MOVX and MOVC. All or part of the Stack
    may be in this area.
    IDATA
    Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
    indirect addressing using instructions other than MOVX and MOVC. All or part of the
    Stack may be in this area. This area includes the DATA area and the 128 bytes
    immediately above it.
    SFR
    Selected CPU registers and peripheral control and status registers, accessible only
    via direct addressing.
    XDATA (P89LPC935/936)
    ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
    addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
    space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip
    XDATA memory.
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    參數(shù)描述
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    P89LPC936FDH518 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TS 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-28 制造商:NXP 功能描述:
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