參數(shù)資料
型號: P89LPC933HDH,512
廠商: NXP Semiconductors
文件頁數(shù): 16/77頁
文件大?。?/td> 0K
描述: IC 80C51 MCU 4KB FLASH 28TSSOP
標準包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 4x8b; D/A 1x8b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8746-5
P89LPC933HDH,512-ND
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P8
9LPC
933_9
34_9
35_9
36
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.V
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ct
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Rev
.8
12
Jan
uary
201
1
23
o
f77
N
X
P
Semi
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s
P89LPC933/934/935/936
8-
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80C5
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[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[4]
The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[5]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[6]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7]
The only reset source that affects these SFRs is power-on reset.
TL2
CCU timer low
CCH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
0000 0000
TOR2H
CCU reload register high
CFH
00
0000 0000
TOR2L
CCU reload register low
CEH
00
0000 0000
TPCR2H
Prescaler control register high
CBH
----
--
TPCR2H.
1
TPCR2H.
0
00
xxxx xx00
TPCR2L
Prescaler control register low
CAH
TPCR2L.
7
TPCR2L.
6
TPCR2L.
5
TPCR2L.
4
TPCR2L.
3
TPCR2L.
2
TPCR2L.
1
TPCR2L.
0
00
0000 0000
TRIM
Internal oscillator trim register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 6.
Special function registers - P89LPC935/936 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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